XC5210-5PQ208C

Product Summary

The XC5210-5PQ208C Field-Programmable Gate Array is engineered to deliver low cost. Building on experiences gained with three previous successful SRAM FPGA fami- lies, the XC5210-5PQ208C brings a robust feature set to pro-(TM) grammable logic design. The VersaBlock logic module, the VersaRing I/O interface, and a rich hierarchy of inter-connect resources combine to enhance design flexibility and reduce time-to-market. The XC5210-5PQ208C is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, sche- matic capture, VHDL, and Verilog HDL synthesis.

Parametrics

Absolute maximum ratings: (1)VCC, Supply voltage relative to GND: -0.5 to +7.0 V; (2)VIN, Input voltage with respect to GND: -0.5 to VCC +0.5 V; (3)VTS, Voltage applied to 3-state output: -0.5 to Vcc +0.5 V; (4)TSTG, Storage temperature (ambient): -65 to +150 ℃; (5)TSOL, Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm): +260 ℃; (6)TJ, Junction temperature in plastic packages: +125℃; (7)Junction temperature in ceramic packages: +150 ℃.

Features

Features: (1)Low-cost, register/latch rich, SRAM based reprogrammable architecture; (2)0.5m m three-layer metal CMOS process technology; (3)256 to 1936 logic cells (3,000 to 23,000 “gates”); (4)Price competitive with Gate Arrays; (5)System Level Features; (6)System performance beyond 50 MHz; (7)6 levels of interconnect hierarchy (TM); (8)VersaRing I/O Interface for pin-locking; (9)Dedicated carry logic for high-speed arithmetic functions; (10)Cascade chain for wide input functions; (11)Built-in IEEE 1149.1 JTAG boundary scan test circuitry on all I/O pins; (12)Internal 3-state bussing capability; (13)Four dedicated low-skew clock or signal distribution nets; (14)Versatile I/O and Packaging(TM); (15)Innovative VersaRing I/O interface provides a high logic cell to I/O ratio, with up to 244 I/O signals; (16)Programmable output slew-rate control maximizes performance and reduces noise; (17)Zero Flip-Flop hold time for input registers simplifies system timing; (18)Independent Output Enables for external bussing; (19)Footprint compatibility in common packages within the XC5200 Series and with the XC4000 Series; (20)Over 150 device/package combinations, including advanced BGA, TQ, and VQ packaging available; (21)Fully Supported by Xilinx Development System; (22)Automatic place and route software; (23)Wide selection of PC and Workstation platforms; (24)Over 100 3rd-party Alliance interfaces; (25)Supported by shrink-wrap Foundation software.

Diagrams